(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to increase the performance of complementary metal oxide semiconductor (CMOS), devices, via the use of a channel region comprised in part with a strained silicon-germanium layer
(2) Description of Prior Art
An attractive approach for increasing CMOS transistor performance is the use of a silicon germanium (SiGe), layer located in the channel region of the CMOS device. The biaxial stress in the SiGe layer, creating strain induced band structure modification, allows enhanced transport properties of electrons for N channel (NMOS), devices, and enhanced transport properties of holes for P channel (PMOS), devices, to be realized. However the ability to place a SiGe layer in a region that will subsequently underlay the gate structure, as well as to subsequently accommodate shallow source/drain regions, can be challenging in terms of integrating the SiGe devices into a conventional CMOS process.
This invention will teach a process in which a SiGe layer is selectively grown on only the active device regions, eliminating the need for costly patterning procedures to remove portions of the SiGe layer overlying non-active device regions, such as insulator filled shallow trench regions. This invention will also describe a composite layer comprised with silicon layers overlying as well as underlying the SiGe component of the composite layer. The silicon layer overlying the SiGe layer, silicon cap layer, allows a gate insulator layer to be thermally grown consuming only a portion of the silicon cap layer. In addition, this invention will also describe the thickness and composition of the silicon cap, SiGe and silicon buffer layers, needed to accommodate the biaxial compressive strain needed for enhanced hole mobility in the PMOS channel region, and the strain induced energy splitting in the conduction band allowing enhanced electron transport properties to enhance electron velocity overshoot in the channel region of NMOS devices. Prior art, such as Ismail et al, in U.S. Pat. No. 5,534,713, describe the use of thick buffer layers, used with a SiGe layer, however the use of these thick layers may not allow for the easy integration into a conventional CMOS process as this present invention does.
It is an object of this invention to fabricate CMOS devices using a SiGe layer as a component of the channel region of a CMOS device.
It is another object of this invention to selectively grow on active device regions only, a composite silicon layer, comprised of a thin underlying silicon buffer layer, a thin SiGe layer, and an overlying, thin silicon cap layer.
It is still another object of this invention to incorporate between about 20 to 40 weight percent germanium (Ge), into the thin SiGe layer to obtain the desired stress characteristic for carrier mobility enhancement, without inducing junction leakage.
In accordance with the present invention a method of fabricating CMOS devices featuring a channel region comprised with a selectively grown, composite silicon layer, which in turn is comprised with a SiGe layer sandwiched between thin silicon layers, is described. After formation of shallow trench isolation (STI) regions in portions of a semiconductor substrate, an P well region is formed in a first region of the semiconductor substrate to be used for the NMOS devices while an N well region is formed in a second portion of the semiconductor substrate for accommodation of PMOS devices. A composite silicon layer is next selectively grown on regions of the semiconductor substrate not occupied by the STI regions. The composite silicon layer is comprised of an optional underlying silicon layer, a SiGe layer with a weight percent between about 20 to 40, and an overlying capping, silicon layer. A silicon dioxide gate insulator layer is next grown consuming a portion of the overlying, capping silicon layer, followed by deposition of, and patterning of, an undoped polysilicon layer, resulting in the formation of polysilicon gate structures for both NMOS and PMOS devices. After formation of lightly doped source/drain regions or extensions, in regions of the composite silicon layer not covered by the gate structures, insulator spacers are formed on the sides of the gate structures. An ion implantation procedure is then employed to place the desired P and N type ions in portions of the semiconductor structure not covered by the gate structures or by the insulator spacers, followed by a rapid thermal anneal (RTA) procedure, used to activate the P and N type ions, creating an N type, heavily doped source/drain region in a portion of the P well region, used for the NMOS devices, and creating a P type, heavily doped source/drain region in a portion of the N well region, for the PMOS devices. The implantation and anneal procedures used to form the heavily doped source/drain regions also results in the doping of the exposed polysilicon gate structures. Formation of metal silicide on the surface of gate structures and source/drain regions is then performed.
A second embodiment of this invention features the growth of an non-selective composite silicon layer, again comprised with the identical SiGe layer described in the first embodiment. The composite silicon layer is comprised of an optional underlying silicon layer, a SiGe layer, and an overlying silicon layer. Portions of the composite silicon layer located on the top surface of non-active regions, need to be selectively removed using photolithographic and dry etching procedures. In addition an optional modification used with the first embodiment entails the insulator filling of V-grooves located at the interface of the tapered top portion an STI regions, and the tapered sides of the selectively deposited composite silicon layer. This is accomplished post-deposition of the composite silicon layer via deposition of an insulator layer followed by a blanket dry etch procedure resulting in a smooth top surface topography featuring the insulator filled, V-groove shapes.